Altera Stratix® 10 FPGA & SoC FPGA
Altera Stratix® 10 FPGA and SoC FPGA significantly improve performance, power efficiency, density, and system integration. Altera Stratix 10 utilizes Altera's innovative Hyperflex™ FPGA architecture, combining technologies like the Embedded Multi-Die Interconnect Bridge (EMIB), Advanced Interface Bus (AIB), and chiplets. As a result, Altera Stratix 10 devices can achieve up to 2X better performance compared to the previous-generation high-performance FPGAs.
Altera Stratix 10 GX FPGA
Designed to meet the high-performance demands of high-throughput systems.
Altera Stratix 10 SX SoC FPGA
Features a hard processor system with a 64-bit quad-core Arm® Cortex-A53 processor.
Altera Stratix 10 TX FPGA
Delivers the most advanced transceiver capabilities in the industry by combining H- and E-transceiver tiles.
Altera Stratix 10 MX FPGA
Essential multi-function accelerator for high-performance computing (HPC).
Altera Stratix 10 DX FPGA
Supports Altera Ultra Path Interconnect for direct coherent connection to future select Altera Xeon Scalable processors.
Altera Stratix 10 NX FPGA
Designed to meet the high-performance demands of high-throughput systems.
Altera Stratix 10 AX FPGA
Delivers direct RF capabilities by integrating high-performance data converters.
Features
- Leverage 2X core clock frequency performance to obtain throughput breakthroughs
- Use reduced IP size enabled by the Altera Hyperflex FPGA architecture to consolidate designs spanning multiple devices into a single device, reducing power by up to 70% versus previous-generation devices
- Faster clock frequencies to reduce bus widths and reduce intellectual property (IP) size, freeing up additional FPGA resources to add greater functionality
- Boost performance with less routing congestion and fewer design iterations using Hyper-Aware design tools
Applications
- ASIC prototyping for higher productivity by reducing design partitioning complexity using monolithic FPGA fabric
- Cyber security with fMAX over 900MHz allows monitoring of all supported protocols at line rates
- Data center acceleration with UPI for direct coherent connection to future select Altera Xeon scalable processor and PCIe Gen4 x16 along with Altera Hyperflex FPGA architecture, configurable DSP engines, and AI Tensor Blocks to enable breakthrough computational throughput
- fMAX over 700MHz using the Altera Hyperflex FPGA architecture, enabling 400G Ethernet
- Radar with up to 8.6 TFLOPS of IEEE 754-compliant single-precision floating-point performance delivers GPU class performance at a fraction of the power
- OTN/data center interconnect including heterogeneous 3D System-in-Package (SiP) integration of transceiver tiles that deliver 30G backplane support with a path to 57.8Gbps and 28.9Gbps
Specifications
- Quad-core Arm Cortex–A53 MPCore processor cluster up to 1.5GHz
- Vector floating-point unit (VFPU) single and double precision, Arm Neon media processing engine for each processor
- 32KB L1 instruction cache with parity, 32KB L1 data cache with error correction code (ECC)
- 1MB KB shared L2 cache with ECC
- 256KB on-chip RAM
- System memory management unit enables a unified memory model and extends hardware virtualization into peripherals implemented in the FPGA fabric
- Cache coherency unit provides one-way (I/O) coherency that allows a CCU master to view the coherent memory of the Arm Cortex–A53 MPCore CPUs
- 8-channel direct memory access (DMA)
- 3X 10/100/1000 EMAC with integrated DMA
- 2X USB OTG with integrated DMA
- 2X UART 16550 compatible
- 4X Serial Peripheral Interface (SPI) controller
- 5X I2C
- 1X eMMC 4.5 with DMA and CE-ATA support SD/SDIO/MMC controller
- 1X ONFI 1.0 or later 8 and 16-bit support NAND flash controller
- Maximum 48 software-programmable GPIO
- 4X general-purpose timers, 4X watchdog timers
- System manager contains memory-mapped control and status registers and logic to control system-level functions and other HPS modules
- Reset manager resets signals based on reset requests from sources in the HPS and FPGA fabric and software writing to the module reset control registers
- Clock manager provides software-programmable clock control to configure all clocks generated in the HPS
SoC FPGA Block Diagram
Videos
Development Kits
Altera Kits de desarrollo Stratix® 10
Entornos completos de diseño para evaluar las capacidades de las FPGA de Stratix 10.
Altera Stratix® 10 GX Signal Integrity Development Kits
A complete design environment with all hardware and software needed to develop Stratix® 10 GX FPGAs.
Altera Stratix® 10 TX Signal Integrity Development Kits
Complete design environment with hardware and software for developing Stratix 10 TX FPGA designs.
Terasic Technologies Stratix® 10 Sensor Processing Kit
High-performance platform designed for real-time sensor data processing and transmission.
Design Software
Altera Quartus® Prime Design Software
Multi-platform design environment for all phases of FPGA and CPLD design.
Altera FPGA AI Suite
Development platform designed to streamline the creation of AI inference solutions on FPGAs.