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Lattice Semiconductor ispPAC®-POWR1014/A Power Manager II

Lattice Semiconductor ispPAC®-POWR1014/A Power Manager II is a general-purpose power supply monitor and sequence controller that incorporates both in-system programmable logic and in-system programmable analog functions implemented in a non-volatile E2CMOS® technology. The ispPAC-POWR1014/A device provides 10 independent analog input channels to monitor up to 10 power supply test points. In addition, the ispPAC®-POWR1014/A provides 14 open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and general-purpose logic interface functions. This device also incorporates a 24-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions.

The on-chip 10-bit analog-to-digital converter is used to monitor the VMON voltage through the I2C bus or JTAG interface of the ispPAC-POWR1014A device. The I2C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the VMON inputs, read back the status of each of the VMON comparator and PLD outputs, control logic signals IN2 to IN4 and control the output pins (ispPAC-POWR1014A only). The JTAG interface can be used to read out all I2C registers during manufacturing.

Features

  • 2-Wire (I2C/SMBus™ compatible) interface
    • Comparator status monitor
    • ADC readout
  • 3.3V Operation, wide supply Range 2.8V to 3.96V
    • -40°C to +85°C Industrial temperature range
    • 48-pin TQFP package, lead-free option
  • Multi-Function JTAG Interface
    • In-system programming
    • Access to all I2C registers
    • Direct input control
  • Monitor and control multiple power supplies
    • Simultaneously monitors up to 10 power supplies
    • Provides up to 14 output control signals
  • Embedded PLD for sequence control
    • 24-macrocell CPLD implements both state machines and combinatorial logic functions
  • Embedded Programmable Timers
    • Four independent timers
    • 32µs to 2 second intervals for timing sequences
  • Analog input monitoring
    • 10 independent analog monitor inputs
    • Two programmable threshold comparators per analog input
  • High-voltage FET drivers
    • Power supply ramp up/down control
    • Programmable current and voltage output

Block Diagram

Lattice Semiconductor ispPAC®-POWR1014/A Power Manager II
Publicado: 2012-03-23 | Actualizado: 2022-03-11