Microchip Technology LAN9646 6-Port Gigabit Ethernet Switch
Microchip Technology LAN9646 6-Port Gigabit Ethernet Switch is a fully integrated, managed Layer 2, six-port gigabit Ethernet switch with advanced features. The Microchip Technology LAN9646 has four ports that support 10/100/1000Mbps PHYs, while the other two are configurable as SGMII, RGMII, MII, or RMII interfaces, allowing connection to a host processor or external PHY. Full register access is available via SPI, I2C, or optional in-band management through any data port, with PHY register access provided by an MIIM interface.
Security features include IEEE 802.1X port-based authentication and ACL filtering. It also supports power management features like Energy-Efficient Ethernet (EEE) for energy-saving environments.
Features
- Non-blocking wire-speed Ethernet switching fabric
- Full-featured forwarding and filtering control, including Access Control List (ACL) filtering
- IEEE802.1X support (port-based network access control)
- IEEE802.1Q VLAN support for 128 active VLAN groups and the full range of 4096 VLAN IDs
- IEEE802.1p/Q tag insertion or removal on a per-port basis and support for double-tagging
- VLAN ID tag/untag options on a per-port basis
- IEEE802.3x full-duplex flow control and half-duplex backpressure collision control
- IGMPv1/v2/v3 snooping for multicast packet filtering
- IPv6 multicast listener discovery (MLD) snooping
- QoS/CoS packets prioritization support: 802.1p, DiffServ-based and re-mapping of 802.1p priority field per-port basis on four priority levels
- IPv4/IPv6 QoS support
- Programmable rate limiting at ingress and egress ports
- Broadcast storm protection
- Four priority queues with dynamic packet mapping for IEEE802.1p, IPv4 DIFFSERV, IPv6 TrafficClass
- MAC filtering function to filter or forward unknown unicast, multicast, and VLAN packets
- Self-address filtering for implementing ring topologies
- High-speed SPI (4-wire, up to 50MHz) interface to access all internal registers
- I2C interface to access all registers
- MII management (MIIM, MDC/MDIO 2 wire) interface to access all PHY registers per IEEE 802.3 specification
- In-band management to access all registers via any of the seven ports, strap-enabled
- I/O pin strapping facility to set certain register bits from I/O pins at reset time
- Control registers configurable on-the-fly
- Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII/RMII
- MIB counters for fully-compliant statistics gathering (34 MIB counters per port)
- Full-chip software power-down
- Energy detect power-down (EDPD)
- Wake on LAN (WoL) support
Applications
- Stand-alone 10/100/1000Mbps Ethernet switches
- VoIP infrastructure switches
- Broadband gateways/firewalls
- Wi-Fi access points
- Integrated DSL/cable modems
- Security/surveillance systems
- Industrial control/automation switches
- Networked measurement and control systems
Additional Resources
- Errata: LAN9646 Silicon Errata and Data Sheet Clarification
- Application Notes: AN3455- 1000BASE-T Transmitter Distortion
- Application Notes: AN1120- Ethernet Theory of Operation
- Application Notes: AN2054- Gigabit Ethernet Guide
- Application Notes: AN2157- Transient Protection in Power Over Ethernet Applications
Publicado: 2024-09-27
| Actualizado: 2024-10-01