Microchip Technology ProASIC3 Flash FPGAs

Microchip ProASIC3 Flash FPGAs offer higher performance and density and features beyond those of the ProASIC^PLUS® family. These FPGAs incorporate non-volatile flash technology that instantly brings the secure, low-power, and single-chip solution. The ProASIC3 flash FPGAs enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. These devices offer 1kb of on-chip, reprogrammable, non-volatile FlashROM storage, and clock conditioning circuitry based on an integrated Phase-Locked Loop (PLL). The ProASIC3 devices support the ARM-Cortex-M1 soft processor IP core that offers benefits of programmability and time-to-market. These Flash FPGAs are ideally used in consumer, industrial, communications, medical, and automotive applications.

Features

High capacity:
- 15K to 1M system gates
- Up to 144Kb of true dual-port SRAM
- Up to 300 users I/Os
Reprogrammable flash technology:
- 130nm, 7-layer metal (6 copper), flash-based CMOS process
- Instant on level 0 support
- Single-chip solution
- Retains programmed design when powered off
High-performance:
- 350MHz system performance
- 3.3V, 66MHz 64-Bit PCI
In-System Programming (ISP) and Security:
- ISP using on-chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM^®-enabled ProASIC^®3 devices) via JTAG (IEEE 1532–compliant)
- FlashLock^® to secure FPGA contents
Low-power:
- Core voltage for low-power
- Support for 1.5V-only systems
- Low-impedance flash switches
High-performance routing hierarchy:
- Segmented, hierarchical routing, and clock structure
Embedded Memory:
- 1Kb of FlashROM user non-volatile memory
- SRAMs and FIFOs with variable-aspect-ratio 4608-Bit RAM
- Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
- True dual-port SRAM (except ×18)

Advanced I/O:
- 700Mbps DDR, LVDS-capable I/Os (A3P250 and above)
- 1.5V, 1.8V, 2.5V, and 3.3V mixed-voltage operation
- Wide range power supply voltage support per JESD8-B, allowing I/Os to operate from 2.7V to 3.6V
- Bank-selectable I/O voltages up to 4 banks per chip
- Single-ended I/O standards: LVTTL, LVCMOS 3.3V/2.5V/1.8V/1.5V, 3.3V PCI/3.3V PCI-X, and LVCMOS 2.5V/5V input
- Differential I/O standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)
- I/O registers on input, output, and enable paths
- Hot-swappable and cold-sparing I/Os
- Programmable output slew rate and drive strength
- Weak pull-up/pull-down
- IEEE 1149.1 (JTAG) boundary-scan test
- Pin-compatible packages across the ProASIC3 family
Clock Conditioning Circuit (CCC) and PLL:
- Six CCC blocks and one with an integrated PLL
- Configurable phase-shift, multiply/divide, delay capabilities, and external feedback
- 1.5MHz to 350MHz wide input frequency range
ARM processor support in ProASIC3 FPGAs:
- M1 ProASIC3 devices - ARM^®Cortex^®-M1 soft processor available with or without debug