Texas Instruments OMAP5910 Dual-Core Applications Processor
Texas Instruments OMAP5910 Dual-Core Applications Processor is a highly integrated hardware and software platform designed to meet the application processing needs of next-generation embedded devices. The OMAP™ platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture benefits DSP and RISC technologies, incorporating a TMS320C55x DSP core and a high-performance TI925T ARM core. The Texas Instruments OMAP5910 is designed to run leading open and embedded RISC-based operating systems and the Texas Instruments (TI) DSP/BIOS™ software kernel foundation. The device is available in a 289-ball MicroStar BGA package.
Features
- Low-power, high-performance CMOS technology
- 0.13µm technology
- 1.6V core voltage
- TI925T (MPU) ARM9TDMI™ core
- Support 32-bit and 16-bit (Thumb® Mode) instruction sets
- 16Kbyte instruction cache
- 8Kbyte data cache
- Data and program Memory Management Units (MMUs)
- Two 64-entry Translation Look-Aside Buffers (TLBs) for MMUs
- 17-word write buffer
- TMS320C55x™ (C55x™) DSP core
- One/two instructions are executed per cycle
- Dual multipliers (two multiply-accumulates per cycle)
- Two arithmetic/logic units
- One internal program bus
- Five internal data/operand buses (three read buses and two write buses)
- 32K x 16-bit on-chip dual-access RAM (DARAM) (64Kbytes)
- 48K x 16-bit on-chip single-access RAM (SARAM) (96Kbytes)
- 16K x 16-bit on-chip ROM (32Kbytes)
- Instruction cache (24Kbytes)
- Video hardware accelerators for DCT, IDCT, pixel interpolation, and motion estimation for video compression
- 192Kbytes of shared internal SRAM
- Memory Traffic Controller (TC)
- 16-bit EMIFS external memory interface to access up to 128Mbytes of Flash, ROM, or ASRAM
- 16-bit EMIFF external memory interface to access up to 64Mbytes of SDRAM
- 9-channel system DMA controller
- DSP memory management unit
- Endianism conversion logic
- Digital Phase-Locked Loop (DPLL) for MPU/DSP/TC clocking control
- DSP peripherals
- Three 32-bit timers and a watchdog timer
- Level1/Level2 interrupt handlers
- Six-channel DMA controller
- Two multichannel buffered serial ports
- Two multichannel serial interfaces
- TI925T peripherals
- Three 32-bit timers and a watchdog timer
- 32kHz timer
- Level1/Level2 interrupt handlers
- USB (full/low speed) host interface with up to 3 ports
- USB (full speed) function interface
- One integrated USB transceiver for either host or function
- Multichannel buffered serial port
- Inter-Integrated Circuit (I2C) master and slave interface
- Microwire™ serial interface
- Multimedia Card (MMC) and Secure Digital (SD) interface
- HDQ/1-wire® interface
- Camera interface for CMOS sensors
- ETM9 trace module for TI925T debug
- Keyboard matrix interface (6 x 5 or 8 x 8)
- Up to ten MPU general-purpose I/Os
- Pulse-Width Tone (PWT) interface
- Pulse-Width Light (PWL) interface
- Two LED Pulse Generators (LPGs)
- Real-Time Clock (RTC)
- LCD controller with dedicated system DMA channel
- Shared peripherals
- Three Universal Asynchronous Receiver/Transmitters (UARTs) (one supporting SIR mode for IrDA)
- Four interprocessor mailboxes
- Up to 14 shared general-purpose I/Os
- Individual power-saving modes for MPU/DSP/TC
- On-chip scan-based emulation logic
- IEEE Std 1149.1 (JTAG) boundary-scan logic
- Two 289-Ball microStar BGA™ (Ball Grid Array) package options (GZG and GDY suffixes)
Applications
- Applications processing devices
- Mobile communications
- 802.11
- Bluetooth™ wireless technology
- GSM (including GPRS and EDGE)
- CDMA
- Proprietary government and other
- Video and image processing (MPEG4, JPEG, Windows® Media Video, etc.)
- Advanced speech applications (text-to-speech, speech recognition)
- Audio processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, and other GSM speech codecs)
- Graphics and video acceleration
- Generalized web access
- Data processing (fax, encryption/decryption, authentication, signature verification, and watermarking)
Functional Block Diagram
Publicado: 2020-07-13
| Actualizado: 2024-07-01